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00023 #ifndef __LPC214x_H
00024 #define __LPC214x_H
00025
00026
00027 #define VIC_BASE_ADDR 0xFFFFF000
00028
00029 #define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
00030 #define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
00031 #define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
00032 #define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C))
00033 #define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010))
00034 #define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014))
00035 #define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018))
00036 #define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C))
00037 #define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020))
00038 #define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x030))
00039 #define VICDefVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x034))
00040 #define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100))
00041 #define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104))
00042 #define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108))
00043 #define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C))
00044 #define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110))
00045 #define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114))
00046 #define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118))
00047 #define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C))
00048 #define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120))
00049 #define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124))
00050 #define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128))
00051 #define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C))
00052 #define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130))
00053 #define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134))
00054 #define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138))
00055 #define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C))
00056 #define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200))
00057 #define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204))
00058 #define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208))
00059 #define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C))
00060 #define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210))
00061 #define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214))
00062 #define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218))
00063 #define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C))
00064 #define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220))
00065 #define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224))
00066 #define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228))
00067 #define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C))
00068 #define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230))
00069 #define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234))
00070 #define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238))
00071 #define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
00072
00073
00074 #define PINSEL_BASE_ADDR 0xE002C000
00075 #define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
00076 #define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
00077 #define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
00078
00079
00080 #define GPIO_BASE_ADDR 0xE0028000
00081 #define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
00082 #define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
00083 #define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
00084 #define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C))
00085 #define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))
00086 #define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))
00087 #define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))
00088 #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
00089
00090
00091 #define FIO_BASE_ADDR 0x3FFFC000
00092 #define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
00093 #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
00094 #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
00095 #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
00096 #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
00097 #define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
00098 #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
00099 #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
00100 #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
00101 #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
00102
00103
00104
00105
00106
00107 #define SCB_BASE_ADDR 0xE01FC000
00108
00109
00110 #define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
00111 #define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))
00112 #define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040))
00113
00114
00115 #define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))
00116 #define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))
00117 #define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))
00118 #define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))
00119
00120
00121 #define PLL48CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0))
00122 #define PLL48CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4))
00123 #define PLL48STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8))
00124 #define PLL48FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC))
00125
00126
00127 #define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))
00128 #define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))
00129
00130
00131 #define VPBDIV (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100))
00132
00133
00134 #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
00135 #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
00136 #define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))
00137 #define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))
00138
00139
00140 #define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
00141
00142
00143 #define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
00144
00145
00146 #define TMR0_BASE_ADDR 0xE0004000
00147 #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
00148 #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
00149 #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
00150 #define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))
00151 #define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))
00152 #define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))
00153 #define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))
00154 #define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))
00155 #define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))
00156 #define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))
00157 #define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))
00158 #define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))
00159 #define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))
00160 #define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))
00161 #define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))
00162 #define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))
00163 #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
00164
00165
00166 #define TMR1_BASE_ADDR 0xE0008000
00167 #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
00168 #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
00169 #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
00170 #define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))
00171 #define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))
00172 #define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))
00173 #define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))
00174 #define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))
00175 #define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))
00176 #define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))
00177 #define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))
00178 #define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))
00179 #define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))
00180 #define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))
00181 #define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))
00182 #define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))
00183 #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
00184
00185
00186 #define PWM_BASE_ADDR 0xE0014000
00187 #define PWMIR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x00))
00188 #define PWMTCR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x04))
00189 #define PWMTC (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x08))
00190 #define PWMPR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x0C))
00191 #define PWMPC (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x10))
00192 #define PWMMCR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x14))
00193 #define PWMMR0 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x18))
00194 #define PWMMR1 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x1C))
00195 #define PWMMR2 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x20))
00196 #define PWMMR3 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x24))
00197 #define PWMMR4 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x40))
00198 #define PWMMR5 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x44))
00199 #define PWMMR6 (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x48))
00200 #define PWMEMR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x3C))
00201 #define PWMPCR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x4C))
00202 #define PWMLER (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x50))
00203
00204
00205 #define UART0_BASE_ADDR 0xE000C000
00206 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00207 #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00208 #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
00209 #define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00210 #define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))
00211 #define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00212 #define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))
00213 #define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))
00214 #define U0MCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x10))
00215 #define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))
00216 #define U0MSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x18))
00217 #define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))
00218 #define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))
00219 #define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))
00220 #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
00221
00222
00223 #define UART1_BASE_ADDR 0xE0010000
00224 #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00225 #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00226 #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
00227 #define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00228 #define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))
00229 #define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00230 #define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))
00231 #define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))
00232 #define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))
00233 #define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))
00234 #define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))
00235 #define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))
00236 #define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))
00237 #define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))
00238 #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
00239
00240
00241 #define I2C0_BASE_ADDR 0xE001C000
00242 #define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
00243 #define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
00244 #define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
00245 #define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))
00246 #define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))
00247 #define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))
00248 #define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
00249
00250
00251 #define I2C1_BASE_ADDR 0xE005C000
00252 #define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
00253 #define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
00254 #define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
00255 #define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))
00256 #define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))
00257 #define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))
00258 #define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
00259
00260
00261 #define SPI0_BASE_ADDR 0xE0020000
00262 #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
00263 #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
00264 #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
00265 #define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))
00266 #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
00267
00268
00269 #define SSP_BASE_ADDR 0xE0068000
00270 #define SSPCR0 (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x00))
00271 #define SSPCR1 (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x04))
00272 #define SSPDR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x08))
00273 #define SSPSR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x0C))
00274 #define SSPCPSR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x10))
00275 #define SSPIMSC (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x14))
00276 #define SSPRIS (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x18))
00277 #define SSPMIS (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x1C))
00278 #define SSPICR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x20))
00279
00280
00281 #define RTC_BASE_ADDR 0xE0024000
00282 #define ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
00283 #define CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
00284 #define CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
00285 #define CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))
00286 #define AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))
00287 #define CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))
00288 #define CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))
00289 #define CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))
00290 #define SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))
00291 #define MINUTES (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))
00292 #define HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))
00293 #define DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))
00294 #define DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))
00295 #define DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))
00296 #define MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))
00297 #define YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))
00298 #define ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))
00299 #define ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))
00300 #define ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))
00301 #define ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))
00302 #define ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))
00303 #define ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))
00304 #define ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))
00305 #define ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))
00306 #define PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80))
00307 #define PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
00308
00309
00310 #define AD0_BASE_ADDR 0xE0034000
00311 #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
00312 #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
00313 #define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
00314 #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
00315 #define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))
00316 #define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))
00317 #define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))
00318 #define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))
00319 #define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))
00320 #define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))
00321 #define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))
00322 #define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))
00323
00324 #define ADGSR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x08))
00325
00326 #define AD1_BASE_ADDR 0xE0060000
00327 #define AD1CR (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x00))
00328 #define AD1GDR (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x04))
00329 #define AD1STAT (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x30))
00330 #define AD1INTEN (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x0C))
00331 #define AD1DR0 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x10))
00332 #define AD1DR1 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x14))
00333 #define AD1DR2 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x18))
00334 #define AD1DR3 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x1C))
00335 #define AD1DR4 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x20))
00336 #define AD1DR5 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x24))
00337 #define AD1DR6 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x28))
00338 #define AD1DR7 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x2C))
00339
00340
00341 #define DAC_BASE_ADDR 0xE006C000
00342 #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
00343
00344
00345 #define WDG_BASE_ADDR 0xE0000000
00346 #define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
00347 #define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
00348 #define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
00349 #define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
00350
00351
00352 #define USB_BASE_ADDR 0xE0090000
00353
00354 #define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
00355 #define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
00356 #define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08))
00357 #define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C))
00358 #define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C))
00359
00360
00361 #define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30))
00362 #define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34))
00363 #define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38))
00364 #define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C))
00365 #define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40))
00366
00367
00368 #define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44))
00369 #define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48))
00370 #define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C))
00371
00372
00373 #define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10))
00374 #define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14))
00375
00376
00377 #define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18))
00378 #define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C))
00379 #define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20))
00380 #define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24))
00381 #define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28))
00382
00383
00384 #define DMA_REQ_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0x50))
00385 #define DMA_REQ_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0x54))
00386 #define DMA_REQ_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0x58))
00387 #define UDCA_HEAD (*((volatile unsigned long *)USB_BASE_ADDR + 0x80))
00388 #define EP_DMA_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0x84))
00389 #define EP_DMA_EN (*((volatile unsigned long *)USB_BASE_ADDR + 0x88))
00390 #define EP_DMA_DIS (*((volatile unsigned long *)USB_BASE_ADDR + 0x8C))
00391 #define DMA_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0x90))
00392 #define DMA_INT_EN (*((volatile unsigned long *)USB_BASE_ADDR + 0x94))
00393 #define EOT_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0xA0))
00394 #define EOT_INT_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0xA4))
00395 #define EOT_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xA8))
00396 #define NDD_REQ_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0xAC))
00397 #define NDD_REQ_INT_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0xB0))
00398 #define NDD_REQ_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xB4))
00399 #define SYS_ERR_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0xB8))
00400 #define SYS_ERR_INT_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0xBC))
00401 #define SYS_ERR_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xC0))
00402 #define MODULE_ID (*((volatile unsigned long *)USB_BASE_ADDR + 0xFC))
00403
00404 #endif // __LPC214x_H
00405